1. Field of the Invention
The present invention relates generally to self-test architectures to implement data column redundancy in a Random Access Memory (RAM), either a Dynamic RAM (DRAM) or a Static RAM (SRAM), and is particularly applicable to compileable memories which are memories designed and compiled from basic building blocks termed kernels. The present invention is also particularly applicable to embedded RAM (eRAM) within microprocessor or logic chips, although it also has applicability to stand alone RAM chips.
More particularly, the subject invention pertains to self-test architectures to implement data column redundancy in a RAM memory that uses column and row redundancy with a totally integrated self-test and repair capability. A specific embodiment of a compileable 1-port SRAM is disclosed, although as noted the present invention has wider applicability to RAM memories in general, and in SRAM memories has wider applicability to dual-port or multi-port SRAM memories.
2. Discussion of the Prior Art
Compileable memories are memories which are custom designed and compiled from basic building blocks termed kernels. Compileable memories are designed or specified to have designated parameters of number of words, word width, and number of bitlines. With those parameters being specified, the design of the compileable memory is then assembled from the building block kernels.
The prior art has used many implementations of redundancy in embedded memories using both spare rows and spare columns. When using both row and column redundancy, a circuit designer must decide how best to implement the repair solution, such that the repair makes optimum use of the spare rows and columns. Some compileable memories have offered spare columns, but have offered no support for self-test, redundancy allocation or steering multiplexors. These memories simply compile an additional data column. For example, if a customer orders a 128K×32 memory, the compiler actually gives the customer a 128K×33 memory. The customer then has to figure out how to test and find the bad column, and also has to implement the steering logic as well as the fusing support circuits.
The prior art has also provided recent developments within ASICs to include row redundancy in compileable memories.